FIG. 1 shows a conventional multiport RAM memory device, in which a RAM memory device 1* has a multiplicity of ports. In accordance with FIG. 1, in this case data input signals DIN are stored via a write port 40 (WP) in memory cells (not illustrated) of the RAM memory device 1*. For separate read-out via a multiplicity of ports, associated address signals Adr0 to Adr3 are applied for example to address/control ports 20, 21, 22 and 23 (ACP), corresponding data output signals DOUT0 to DOUT3 being output at associated read ports 30, 31, 32 and 33 (RP). In this way, a multiplicity of drive units can access the individual memory cells in the RAM memory device via the multiplicity of ports. The RAM memory device is in this case a random access memory device (RAM).
One disadvantage in conventional multiport RAM memory devices is that there is an extremely high area requirement and outlay on wiring. The production costs of such a multiport RAM memory device, in particular as an integrated module, are therefore extremely high. Furthermore, the power loss of such a hardwired multiport RAM memory device is extremely high, for which reason it cannot be used in particular in switching networks for the realization of the speech memories situated therein.
DE 197 09 210 A1 discloses a RAM memory circuit as is illustrated in a simplified fashion in FIG. 2. In this case, a multiport RAM memory device or memory device with multiple ports is created using a so-called single port RAM memory unit 1 (single port RAM), a multiplexer unit M and a multiplicity of buffer devices P. In this case, via a bidirectional data bus, both the data input signals and the data output signals are transferred from the respective buffers P to the write port 4 or read port 3 of the single port RAM memory unit 1. The multiplexer M switches through one of the multiplicity of address signals Adr0 to Adr3 to the common address/control port 2 of the RAM memory unit 1 in a manner dependent on a clock supply T. A RAM memory device with a multiplicity of ports is obtained using a cost-effective single port RAM memory unit 1 (single port RAM). However, there is a relatively low data throughput and occurrence of bus contentions on the bidirectional data bus. Furthermore, a power consumption of such a conventional multiport RAM memory device is extremely high.